This invention relates, in general, to switched capacitor circuits, and more particularly, to reducing voltage error when charging and discharging a capacitor through a transmission gate.
In an integrated circuit, switches for coupling one element to another are formed from transistors. One type of switch formed from transistors is known as a transmission gate. A transmission gate formed in a Complementary Metal Oxide Semiconductor (CMOS) wafer process flow is well known and comprises a n and p-channel enhancement MOSFET (Metal Oxide Semiconductor Field Effect Transistors).
A transmission gate made from both n and p-channel enhancement MOSFETs is capable of coupling a voltage approaching either power supply voltage of a circuit to a storage element. A transmission gate is enabled and disabled by a control signal and a complementary control signal. An enabled transmission gate has a finite resistance that corresponds to transistor size (W/L ratio). For example, increasing transistor size (W/L ratio) of a transmission gate reduces resistance. A disabled transmission gate has an extremely high impedance and approximates an open circuit.
A switched capacitor network typically comprises transmission gates, capacitors, and active circuits such as amplifiers. Transmission gates are used to couple one element to another. In particular, a transmission gate is effective in coupling a voltage to a capacitor for storing charge. The capacitor is charged and discharged through the transmission gate. Ideally, a voltage applied to a transmission gate is transferred and stored on a capacitor. In practice, the voltage on the capacitor is not identical to the applied voltage. It is well known that the time period for charging and discharging the capacitor, the resistance of the transmission gate, and charge coupling due to parasitic capacitance of the transmission gate, affect the resultant voltage on the capacitor.
It would be of great benefit if a circuit and method for reducing voltage error when charging and discharging a capacitor through a transmission gate could be provided for enhancing switched capacitor network performance.